1. Technical Field
The inventive concept relates to a semiconductor device, and more particularly, to a resistive memory device and a method of fabricating the same.
2. Related Art
Nonvolatile memory devices, of which phase-change memory devices, flash memory devices, magnetic memory devices, and the like are representative, tend to be highly integrated with low cost based on multi-level cell technology.
The phase-change memory device among the nonvolatile memory devices are becoming practical alternatives to limitations for scaling of dynamic random access memories (DRAMs) and reliability of flash memory devices. In particular, the phase-change memory devices have advantages of nonvolatile characteristic, a high speed operation, stability, a non-erase operation, endurance, and access in units of bytes and therefore may be referred to as next-generation memory devices which are most suitable for storage class memories (SCMs).
The SCMs are applied as storage apparatus and/or main memory apparatus and the phase-change memory devices have to perform program and read operation fast and accurately with low power consumption so as to perform the functions.
Further, the phase-change memory devices have been developed in a multi-level cell (MLC) structure from a single-level cell (SLC) structure so as to be highly integrated. The method of controlling a pulse applied to a memory cell having the same structure as the SLC is mainly used so as to implement the MLC.
FIG. 1 is view illustrating a structure of a phase-change memory device.
As shown in FIG. 1, a switching device 103 is formed on a semiconductor substrate 101 in which a bottom structure is formed and a lower electrode 105 is formed to be electrically connected to the switching device 103. A phase-change material pattern 107 and an upper electrode 109 are formed on the lower electrode 105 and the upper electrode 109 is electrically connected to a bit line (not shown) through a contact plug 111.
FIG. 2 is a view illustrating an example of a pulse applied so as to cause a memory device having the structure of FIG. 1 to operate in the MLC.
First, FIG. 2(a) shows a single pulse mode and implements the MLC through a write-read process. In this pulse applying method, the applied pulse type is simple, but transition state between a “10” state and a “01” state is inaccurate.
FIG. 2(b) shows a first double pulse mode and implements the MLC through a reset current application—a write-read process. In this pulse applying method, a reset pulse is applied in advance before applying a program pulse so as to program a “10” state and a “01” state. Therefore, additional pulse is necessary in addition to a single pulse mode as shown in FIG. 2(a) and three pulse levels are necessary. However, an intermediate level such as “01” and “10” is easily formed.
Next, FIG. 2(c) shows a second double pulse mode. This pulse applying method is similar to the first double pulse mode in that a reset pulse is applied in advance before applying a program pulse so as to program a “10” state and a “01” state. However, the pulse applying method is different from the first double pulse mode in that a program pulse, which is applied to form an intermediate level, is configured in a slow quench type. This pulse applying method uses one pulse level and thus a configuration for a voltage pumping circuit can be simplified.
FIG. 2(d) shows a third double pulse mode and implements the MLC though a set current application-write-read process. This pulse applying method is similar to the method of FIG. 2(b). However, the pulse applying method is different from the method of FIG. 2(b) in that a set current is first applied.
FIG. 2(e) shows that the MLC is implemented through a program and verifying mode (PNV). The pulse applying method adds a verifying pulse to a single pulse mode and is the best mode to form a desired resistance state. However, the program period of time becomes long due to repeat of the program and verifying process.
As described above, at present, the MLC is implemented by applying the same cell structure as the cell structure applied to the SLC and changing only the pulse type. Therefore, the data level can be changed according to resistance drift or partial composition change in the phase-change material and, therefore, it is difficult to guarantee reliability due to increase in useful life of the memory device.